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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Analog Multiplexers/ Demultiplexers with Address Latch MC54/74HC4351 MC54/74HC4353 High-Performance Silicon-Gate CMOS The MC54/74HC4351, and MC54/74HC4353 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/ Outputs is to be connected, by means of an analog switch, to the Common Output/Input. The data at the Channel-Select inputs may be latched by using the active-low Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. For multiplexers/demultiplexers without latches, see the HC4051, HC4052, and HC4053. * * * * * * * * Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance than Metal-Gate Types Low Noise In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: HC4351 -- 222 FETs or 55.5 Equivalent Gates HC4353 -- 186 FETs or 46.5 Equivalent Gates 20 1 J SUFFIX CERAMIC PACKAGE CASE 732-03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738-03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D-04 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDW Ceramic Plastic SOIC PIN ASSIGNMENT MC54/74HC4351 X4 X6 NC X X7 X5 ENABLE 1 ENABLE 2 VEE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC X2 X1 X0 X3 A NC B C LATCH ENABLE NC = NO CONNECTION 10/95 (c) Motorola, Inc. 1995 1 REV 6 MC54/74HC4351 MC54/74HC4353 LOGIC DIAGRAM MC54/74HC4351 Single-Pole, 8-Position Plus Common Off and Address Latch 17 X0 18 X1 19 X2 16 X3 1 X4 6 X5 2 X6 5 X7 FUNCTION TABLE MC54/74HC4351 MULTIPLEXER/ DEMULTIPLEXER 4 X COMMON OUTPUT/INPUT Control Inputs Enable 1 2 C Select B A ON Channel (LE = H)* ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS A B C 15 13 12 11 7 8 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 L H L L L X0 L H L L H X1 H L H L L X2 H L H L H X3 L L H L X4 H L L H H X5 H H L H L X6 H H L H H X7 H X X X None X H X L X None X X X = don't care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. BLOCK DIAGRAM MC54/74HC4353 Triple Single-Pole, Double-Position Plus Common Off and Address Latch 16 X0 17 X1 Y0 Y1 Z0 Z1 15 13 12 11 7 8 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 2 1 6 4 PIN ASSIGNMENT X SWITCH 18 X COMMON OUTPUT/INPUT Y1 Y0 NC Z1 Z SWITCH 5 Z Z Z0 ENABLE 1 ENABLE 2 VEE GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Y X X1 X0 A NC B C LATCH ENABLE Y SWITCH 19 Y CHANNEL-SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 NC = NO CONNECTION FUNCTION TABLE Control Inputs Enable 1 L L L L L L L L H X 2 H H H H H H H H X L C L L L L H H H H X X Select B L L H H L L H H X X A L H L H L H L H X X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 On Channel (LE = H)* Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None None X0 X1 X0 X1 X0 X1 X0 X1 NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X Switch, Input B controls the Y Switch, and Input C controls the Z Switch. X = Don't Care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). VCC = 2.0 V 0 1000 ns VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC VEE Tstg VIS Vin PD TL I Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) Storage Temperature Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package DC Current Into or Out of Any Pin DC Input Voltage (Ref. to GND) Analog Input Voltage Negative DC Supply Voltage (Ref. to GND) Positive DC Supply Voltage Parameter (Ref. to GND) (Ref. to VEE) - 1.5 to VCC + 1.5 - 65 to + 150 - 7.0 to + 0.5 - 0.5 to + 7.0 - 0.5 to 14.0 VEE - 0.5 to VCC + 0.5 Value 25 260 300 750 500 Unit mW mA High-Speed CMOS Logic Data DL129 -- Rev 6 DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted RECOMMENDED OPERATING CONDITIONS Symbol Symbol VIO* VCC VEE tr, tf VIS Vin ICC TA VIH VIL Iin Input Rise and Fall Time, Channel Select or Enable Inputs (Figure 9a) Operating Temperature, All Package Types Static or Dynamic Voltage Across Switch Digital Input Voltage (Ref. to GND) Analog Input Voltage Negative DC Supply Voltage Positive DC Supply Voltage Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Parameter Parameter Channel Select = VCC or GND Enables = VCC or GND VIS = VCC or GND VEE = GND VIO = 0 V VEE = - 6.0 Vin = VCC or GND, VEE = - 6.0 V Ron = Per Spec Ron = Per Spec (Ref. to GND) (Ref. to VEE) (Ref. to GND) Test Conditions 3 GND - 6.0 VEE - 55 Min 2.0 2.0 -- + 125 GND VCC VCC 6.0 12.0 Max 1.2 VCC V 6.0 6.0 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Unit _C _C _C V V V V V V V V V MC54/74HC4351 MC54/74HC4353 - 55 to 25_C 0.1 1.5 3.15 4.2 0.3 0.9 1.2 2 8 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the ranges indicated in the Recommended Operating Conditions. Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. See Applications Information. Guaranteed Limit v 85_C v 125_C 1.0 1.5 3.15 4.2 0.3 0.9 1.2 20 80 1.0 1.5 3.15 4.2 40 160 0.3 0.9 1.2 MOTOROLA Unit A A V V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I III I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I III I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I III I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I III I I I I I II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) DC ELECTRICAL CHARACTERISTICS Analog Section MC54/74HC4351 MC54/74HC4353 Symbol Symbol Ron Ron tPLH, tPHL tPLH, tPHL tPLH, tPHL Ion Ioff tPZL, tPZH tPLZ, tPHZ Cin Cl/O CPD Maximum On-Channel Leakage Current, Channel to Channel HC4351 Maximum Off-Channel Leakage Current, Common Channel HC4351 Maximum Off-Channel Leakage Current, Any One Channel Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum "ON" Resistance Maximum Capacitance Analog I/O Maximum Input Capacitance Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) Maximum Propagation Delay, Latch Enable to Analog Output (Figure 12) Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) Power Dissipation Capacitance (Per Package) (Figure 14)* Parameter Common O/I: HC4351 HC4353 HC4353 HC4353 Feedthrough Parameter Vin = VIL or VIH VIS = VCC to VEE IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC - VEE) IS 2.0 mA Vin = VIL or VIH Switch to Switch = VCC - VEE (Figure 5) Vin = VIL or VIH VIO = VCC - VEE Switch Off (Figure 4) Vin = VIL or VIH VIO = VCC - VEE Switch Off (Figure 3) v v v Enable 1 = VIH, Enable 2 = VIL Test Conditions 4 VCC V 6.0 6.0 6.0 6.0 6.0 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- -- -- - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 0.0 - 4.5 - 6.0 0.0 - 4.5 - 6.0 0.0 - 4.5 - 6.0 VEE V - 55 to 25_C - 55 to 25_C 130 50 345 69 59 290 58 49 325 65 55 370 74 63 1.0 35 10 60 12 10 150 100 80 190 120 100 0.1 0.2 0.1 0.2 0.1 30 12 10 Typical @ 25C, VCC = 5.0 V Guaranteed Limit Guaranteed Limit 45 (HC4351) 45 (HC4353) v 85_C v 125_C High-Speed CMOS Logic Data DL129 -- Rev 6 v 85_C v 125_C 130 50 435 87 74 365 73 62 410 82 70 465 93 79 1.0 35 10 75 15 13 190 125 100 240 150 125 1.0 2.0 1.0 2.0 0.5 35 15 12 130 50 515 103 87 435 87 74 485 97 82 550 110 94 1.0 35 10 90 18 15 230 140 115 280 170 140 2.0 4.0 2.0 4.0 1.0 40 18 14 Unit Unit pF pF pF ns ns ns ns ns A A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I III I III I I 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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I * Limits not tested. Determined by design and verified by qualification. NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). High-Speed CMOS Logic Data DL129 -- Rev 6 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Symbol THD BW -- -- -- tr, tf tsu tw th Total Harmonic Distortion (Figure 15) Crosstalk Between Any Two Switches (Figure 13) (Test does not apply to HC4351) Feedthrough Noise, Channel Select Input to Common O/I (Figure 8) Off-Channel Feedthrough Isolation (Figure 7) Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 6) Maximum Input Rise and Fall Times, Channel-Select, Latch Enable, and Enables 1 and 2 Minimum Pulse Width, Latch Enable (Figure 12) Minimum Hold Time, Latch Enable to Channel Select (Figure 12) Minimum Setup Time, Channel-Select to Latch Enable (Figure 12) Parameter Parameter fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A Enable = GND RL = 600 , CL = 50 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF v fin = 1.0 MHz, RL = 50 , CL = 10 pF fin = 1 MHz, RL = 50 , CL = 10 pF Test Condition 5 RL = 10 k, CL = 10 pF VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 1000 500 400 VCC V 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 100 20 17 80 16 14 0 0 0 Guaranteed Limit - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 - 2.25 - 4.50 - 6.00 VEE V 1000 500 400 100 20 17 125 25 21 0 0 0 80 80 80 51 25_C 54/74HC Limit* 0.10 0.08 0.05 - 60 - 60 - 60 - 50 - 50 - 50 - 40 - 40 - 40 - 50 - 50 - 50 35 145 190 25 105 135 95 95 95 52 1000 500 400 120 24 20 150 30 26 0 0 0 MC54/74HC4351 MC54/74HC4353 v 85_C v 125_C 120 120 120 53 MOTOROLA mVPP Unit MHz Unit ns ns ns ns dB dB % MC54/74HC4351 MC54/74HC4353 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 250 200 125C 150 100 - 55C 50 25C 100 80 60 40 20 125C 25C - 55C 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V Figure 1b. Typical On Resistance, VCC - VEE = 4.5 V 105 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 90 75 60 45 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 - 55C 125C 25C 75 60 45 30 15 125C 25C - 55C 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1c. Typical On Resistance, VCC - VEE = 6.0 V Figure 1d. Typical On Resistance, VCC - VEE = 9.0 V PLOTTER 70 Ron , ON RESISTANCE (OHMS) 60 50 40 30 20 10 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 GND ANALOG IN - 55C 125C 25C PROGRAMMABLE POWER SUPPLY - + DEVICE UNDER TEST COMMON OUT MINI COMPUTER DC ANALYZER VCC VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VEE Figure 1e. Typical On Resistance, VCC - VEE = 12.0 V Figure 2. On Resistance Test Set-Up MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4351 MC54/74HC4353 VCC VCC VEE VCC 20 ANALOG I/O A NC VIH 7 8 9 10 OFF OFF VCC VCC VEE VCC 20 ANALOG I/O OFF A OFF VIH 7 8 9 10 COMMON O/I COMMON O/I VEE VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up VCC A ON VEE VCC ANALOG I/O VIL VIH 7 8 9 10 OFF 20 VCC VCC fin COMMON O/I N/C VCC 7 8 9 10 VEE 0.1F ON 20 VOS dB METER CL* RL VEE *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up Figure 6. Maximum On Channel Bandwidth, Test Set-Up VIS 0.1 F fin RL 7 8 9 10 VEE OFF VCC 20 VOS dB METER RL RL ON/OFF ANALOG I/O OFF/ON RL VCC Vin 1 MHz tr = tf = 6 ns 7 8 9 10 20 VCC COMMON O/I RL CL* CL* TEST POINT VCC 11 VCC GND VEE CHANNEL SELECT *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 7. Off Channel Feedthrough Isolation, Test Set-Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up High-Speed CMOS Logic Data DL129 -- Rev 6 7 MOTOROLA MC54/74HC4351 MC54/74HC4353 VCC ON/OFF ANALOG I/O tr CHANNEL SELECT tPLH ANALOG OUT 50% CHANNEL SELECT *Includes all probe and jig capacitance. 90% 50% 10% tPHL tf VCC GND VCC 7 8 9 10 OFF/ON VCC 20 COMMON O/I CL* TEST POINT Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out VCC 20 ANALOG I/O ON ANALOG IN 50% GND tPLH ANALOG OUT 50% *Includes all probe and jig capacitance. tPHL VCC VCC 7 8 9 10 CL* COMMON O/I TEST POINT Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC ENABLE 50% GND tPZL ANALOG OUT ANALOG OUT 50% tPZH 50% tPHZ 10% 90% tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE VCC 1 2 ANALOG I/O ON/OFF CL* ENABLE 7 8 9 10 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 20 1 k TEST POINT Figure 11a. Propagation Delay, Enable 1 or 2 to Analog Out Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out MOTOROLA 8 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4351 MC54/74HC4353 VCC CHANNEL SELECT VCC 50% GND tsu tr LATCH ENABLE 2 90% 50% 10% tw tf th VCC GND ANALOG I/O VCC 7 8 9 10 VCC ON/OFF OFF/ON 20 COMMON O/I CL* TEST POINT 11 LATCH ENABLE COMMON O/I tPLH, tPHL 50% CHANNEL SELECT *Includes all probe and jig capacitance. Figure 12a. Propagation Delay, Latch Enable to Analog Out Figure 12b. Propagation Delay, Test Set-Up Latch Enable to Analog Out VIS RL fin 0.1 F OFF VCC VEE RL 7 8 9 10 ON 20 VCC VOS dB METER RL CL* RL CL* VCC ON/OFF ANALOG I/O VCC 7 8 9 10 VEE VCC A 20 NC OFF/ON COMMON O/I VCC 11 *Includes all probe and jig capacitance. CHANNEL SELECT Figure 13. Crosstalk Between Any Two Switches, Test Set-Up Figure 14. Power Dissipation Capacitance, Test Set-Up 0 VIS 0.1 F fin VCC 7 8 9 10 VEE *Includes all probe and jig capacitance. ON RL CL* - 10 VCC 20 VOS TO DISTORTION METER dB - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 1.0 2.0 FREQUENCY (kHz) 3.125 DEVICE SOURCE FUNDAMENTAL FREQUENCY Figure 15a. Total Harmonic Distortion, Test Set-Up Figure 15b. Plot, Harmonic Distortion High-Speed CMOS Logic Data DL129 -- Rev 6 9 MOTOROLA MC54/74HC4351 MC54/74HC4353 APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = + 5 V = logic high GND = 0 V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal of ten volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts VEE - GND = 0 to - 6 volts VCC - VEE = 2 to 12 volts and VEE v GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (D x ) are recommended as shown in Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping. +5 V +5V -5V 20 ANALOG SIGNAL +5 V 7 8 9 10 -5 V 15 13 12 11 TO EXTERNAL CMOS CIRCUITRY 0 TO 5 V DIGITAL SIGNALS VEE ON ANALOG SIGNAL +5V -5V Dx Dx VCC VCC 20 ON/OFF VCC Dx Dx VEE VEE 9 10 Figure 16. Application Example Figure 17. External Germanium or Schottky Clipping Diodes +5V +5V +5V VEE 20 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V * VCC 7 8 9 10 VEE 15 13 12 11 * 2 k R 10 k R R R R LSTTL/NMOS CIRCUITRY VCC 7 8 9 10 VEE 15 13 12 11 HCT BUFFER LSTTL/NMOS CIRCUITRY +5V VEE +5V VEE 20 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V VEE +5V a. Using Pull-Up Resistors b. Using HCT Interface Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs MOTOROLA 10 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4351 MC54/74HC4353 FUNCTION DIAGRAM HC4351 A 15 LATCH & LEVEL SHIFTER 17 X0 X1 13 LATCH & LEVEL SHIFTER B X2 X3 12 LATCH & LEVEL SHIFTER 6 C X4 LATCH 11 ENABLE ENABLE 1 ENABLE 2 7 LEVEL SHIFTER 8 X5 2 X6 5 X7 4 X FUNCTION DIAGRAM HC4353 A 15 LATCH & LEVEL SHIFTER 17 X1 16 18 B 13 LATCH & LEVEL SHIFTER 1 X0 X Y1 2 19 C 12 LATCH & LEVEL SHIFTER 4 Y0 Y Z1 LATCH 11 ENABLE ENABLE 1 ENABLE 2 7 LEVEL SHIFTER 8 6 5 Z0 Z High-Speed CMOS Logic Data DL129 -- Rev 6 11 MOTOROLA MC54/74HC4351 MC54/74HC4353 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E B A F C L DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 20 1 11 10 N H D SEATING PLANE G K J M -A- 20 11 N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E B 1 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 -T- SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N -A- 20 11 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E 10X -B- 1 10 P 0.010 (0.25) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 20X D M 0.010 (0.25) TA S B J S F R X 45 _ C -T- 18X SEATING PLANE G K M MOTOROLA 12 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC4351 MC54/74HC4353 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 13 *MC54/74HC4351/D* MC54/74HC4351/D MOTOROLA |
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